1. Field of the Invention
The present invention is related to the field of circuit design. In particular, the present invention is related to method and apparatus to create bypass logic in a digital circuit design.
2. Description of the Related Art
The use of pipeline stages in microprocessor design is well known by one having ordinary skill in the art. Pipelining provides for the subdivision of circuit delays across multiple cycles. Pipelines stages have state or memory circuit elements that hold data from a previous pipeline stage's output and makes that data available for input of the next pipeline stage's logical operations. These state or memory circuit elements are constructed many different ways, but are sequentially clocked either unconditionally or conditionally. Some of the conditionally clocked memory elements require multiple pipeline stages to just implement their function. Sometimes data needed by a logical operation in one pipeline stage of logic may be dependent upon the results of a conditional memory pipeline element in another stage of the same or different pipeline. Modern microprocessors provide bypass logic to enable the data to be obtained directly from another pipeline stage, rather than waiting the full pipeline time for it to be written to the final conditional memory element (destination register) and then obtaining the data. Thus, bypass logic bypasses the waiting of the data to actually get to the destination register and the reading of the data from the destination register, and therefore decreases the amount of time for the operation and increases a microprocessor's throughput.
Bypass logic is used to keep a finite-state-machine's (FSM) total latency loop the same as originally described even though the implementation of some of the latencies within the loop take more cycles. These additional latencies are used to ease the implementation of constructing those circuits. Implementation of bypass logic is only useful for design consideration whenever the pipeline stage is conditionally updated or clocked and when the delay of the function is longer than the delay of an implemented logical multiplexer. These conditional pipeline stages typically are register files or other deterministic memory elements (registers). A simple but valid common abstraction of all of these elements may be a common conditionally enabled flip-flop.
Microprocessor designers create logical models, using high-level logic descriptions, to represent the design's behavior. These models are used for the logical validation of the whole design and by the circuit implementation of the microprocessor to constructs the completed final silicon. Implementation diverges from the high-level model details as long as CAD technologies can prove behavioral equivalence. In order to incorporate a bypass logic circuit in a circuit's design, conventionally, the design's high-level logic description includes detailed instructions for implementing the bypass logic circuitry. This is necessary because the methods and computer aided design (CAD) tools do not guarantee proofs for an implementation using a bypass logic circuit without a detailed description of the logic bypass circuit also in the high-level model. Even with a detailed description, the bypass logic may be implemented in other than the optimum location in the circuit's design, and may hinder the circuit's portability and scalability.